1. Field of the Invention
The present invention relates to an interconnection technique around a semiconductor chip and, more particularly, to the interconnection design of a multilayered semiconductor package serving as a semiconductor device having a multilayered structure in which a plurality of semiconductor chips are stacked in a plurality of layers, and a method of manufacturing a semiconductor device having a multilayered structure.
2. Description of the Related Art
Recently, semiconductor devices are integrated more and more. An example of highly integrated semiconductor devices is a so-called multichip package in which one semiconductor device incorporates a plurality of semiconductor chips. Multichip packages include a so-called multilayered semiconductor package constituted by stacking a plurality of semiconductor chips in a plurality of layers. A multilayered semiconductor package manufacturing process generally called an SBM (System Block Module) will be briefly exemplified.
First, one or a plurality of semiconductor chips are mounted on a plurality of chip mounting boards. Each chip mounting board has a plurality of chip interconnections electrically connected to a plurality of terminals of each semiconductor chip. The semiconductor chip is mounted on the chip mounting board by connecting terminals to chip interconnections. The chip mounting board on which a predetermined number of semiconductor chips are mounted is integrated into an interconnection board. In general, the interconnection board is formed to a size enough to mount a plurality of chip mounting boards at once on one interconnection board. The interconnection board has a plurality of intermediate interconnections electrically connected to the terminals of semiconductor chips via chip interconnections formed on chip mounting boards. A plurality of chip mounting boards on each of which a predetermined number of semiconductor chips are mounted are mounted at predetermined positions on an interconnection board by, e.g., a flip chip method so as to electrically connect the chip interconnections of the chip mounting boards to the intermediate interconnections of the interconnection boards.
Then, a predetermined number of interconnection boards on each of which a predetermined number of chip mounting boards are mounted are stacked along the direction of thickness of the interconnection boards. At this time, the interconnection boards are so stacked as to alternately arrange the chip mounting boards and the interconnection boards along the stacking direction. In addition, interconnection boards are so stacked as to electrically connect the chip interconnections of chip mounting boards and the intermediate interconnections of the interconnection boards that are adjacent to each other in the stacking direction. The stacked interconnection boards are integrated by, e.g., thermocompression bonding. Subsequently, an external terminal board and insulating cover are so arranged as to sandwich the integrated interconnection boards from two outer sides in the stacking direction. At this time, the external terminal board is set on a side on which the external terminal board contacts the interconnection board, and the insulating cover is set on a side on which the cover contacts the chip mounting board. The external terminal board and insulating cover are integrated into the interconnection boards integrated by thermocompression bonding.
The external terminal board has a plurality of external terminal interconnections electrically connected to the intermediate interconnections of an adjacent interconnection board. The external terminal interconnection has external terminals for electrically connecting signal paths inside the multilayered semiconductor package to signal paths outside the package. The external terminal board is so arranged as to electrically connect the external terminal interconnections to intermediate interconnections formed on an adjacent interconnection board. The semiconductor chips are electrically connected to wiring lines outside the package by predetermined paths via the chip interconnections, intermediate interconnections, and external terminal interconnections. The semiconductor chips, chip interconnections, and intermediate interconnections inside the package are protected from the outside by the insulating cover and external terminal board.
Finally, the interconnection boards integrated with the external terminal board and insulating cover are divided into a plurality of blocks having a predetermined number of semiconductor chips in each layer. As a result, an SBM (System Block Module) functioning as a desired semiconductor system is obtained.
A semiconductor chip mounted on an SBM formed by the above-described process is formed as, e.g., a memory chip. The memory chip generally has a plurality of data pins as terminals. The data pin must be electrically connected to a wiring line outside a module or the like independently for each data pin of each semiconductor chip in each layer. The signal paths of the data pins are made electrically independent by forming intermediate interconnections into the same pattern in layers and forming chip interconnections into different patterns in the layers. In this case, a chip mounting board to be arranged in a predetermined layer must be so managed as not to be replaced with a chip mounting board to be arranged in another layer. Replacement of chip mounting boards in two arbitrary layers within a module makes the entire SBM defective. This leads to a low SBM yield, and a trouble may occur in the SBM manufacturing process.
From this, when the signal paths of data pins are independently set by the chip interconnections of chip mounting boards, a plurality of chip mounting boards must be managed with extra care. The SBM manufacturing process becomes very cumbersome. This results in a low production efficiency and high manufacturing cost in mass production of SBMs.